1. Field of the Invention
This invention relates to a multi-layer circuit board including a reactance element and a method of trimming a reactance element in a circuit board.
2. Description of the Prior Art
A multi-layer printed circuit board including inductance trimming patterns is known. Japanese patent application provisional publication No. 62-109418 discloses a chip type delay element including an inductance pattern formed on a surface of a dielectric substrate and comb electrodes, wherein the comb electrodes are subjected to a laser cut process to provide a desired delay time.
Japanese patent application provisional publication No. 7-297637 discloses a resonating circuit board including a microstrip conductor as inductance element and a plurality of stab conductors for controlling the line length of the microstrip conductor, a capacitive electrode patterns, and timing conductors for trimming the capacitance of the capacitive electrode patters.